A Dual-Edge Triggered Phase Detector for Fast-Lock DLL
نویسندگان
چکیده
DLL is used as a clock generator due to its stable operation and relatively simple design. Analog DLL has the advantages of lower phase offset and lower clock jitter than digital DLL. However, locking speed is slow in analog DLL. This paper proposes a dual edge triggered phase detector to enhance the locking speed of analog DLL and suggests a closed-form expression of locking speed which can correctly estimate the locking speed. Simulation results show that the locking speed of DLL, which includes the proposed phase detector, is 2~2.5 times better than that of DLL, which includes a single edge triggered phase detector. Key-Words: Dual-Edge Triggered, Dual-Edge Checking, Phase Detector, PD, DLL, Analog DLL, Locking Speed
منابع مشابه
Dual Edge Triggered Phase Detector for DLL and PLL Applications
An ASIC design of Dual Edge Triggered Phase Detector(DET PD) for Delay locked loop(DLL) and Phase locked loop(PLL) applications is proposed in this paper.The proposed DET PD has high locking speed and less jitter. The designs are based on TSPC flip flop logic, which overcomes the issue of narrow capture range. The Double edge triggered phase detector dissipates less power than conventional desi...
متن کاملDual Phase Detector Based Delay Locked Loop for High Speed Applications
In this paper a new architecture for delay locked loops will be presented. One of problems in phase-frequency detectors (PFD) is static phase offset or reset path delay. The proposed structure decreases the jitter resulted from PFD by switching two PFDs. In this new architecture, a conventional PFD is used before locking of DLL to decrease the amount of phase difference between input and outpu...
متن کاملHigh Speed Delay-Locked Loop for Multiple Clock Phase Generation
In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Theref...
متن کاملDesign and Implementation of Fast Locking and Harmonic Free in Multiphase Digital DLL – Robust to Process Variations
An ADMDLL(All Digital Multiphase Delay Locked Loop) with Harmonic free , Low power , Low Jitter and Immune to SSN features are presented. Harmonic Free and Immune to SSN of the proposed ADMDLL are achieved by implementing a Narrow-Wide Coarse Lock Detector (NWCLD) and Time to Digital Converter (TDC),which maintains the delay between reference clock and outgoing clock with in the suitable range ...
متن کاملA BIST Solution for The Test of I/O Speed
A delay-locked loop (DLL) based built-in self test (BIST) circuit has been designed with a 0.18 μ m TSMC process (CM018) to test chip I/O speeds, specifically, the setup and hold times of I/O registers or buffers. The frequency lock range of the DLL is 150-600 MHz (4x). The DLL uses a combined phase detector and charge pump circuit (PD+CP) for increased speed and reduced jitter. The DLL also em...
متن کامل